1. Field
The present disclosure pertains to the field of power management for a processing system and particularly to resuming operations upon exiting a low power state.
2. Description of Related Art
Power management is an increasingly important feature in systems such as computer systems. However, users are generally less interested in power conservation features that significantly impact the response time and performance of their systems. Thus, implementing low power states with low latency resumption is desirable.
The Advanced Configuration and Power Interface (ACPI) Specification 1.0b provides a uniform set of definitions, power management states, and the like for implementing power conservation features in a computing system. The ACPI Specification defines the S1 power state as a low latency power state in which all system context is maintained (see §9.1.1).
A typical system arrangement asserts the STPCLK# pin and waits for the processor to enter the stop grant state. At this point, the system may or may not shut down clocks to the processor and/or to external buses or other circuitry. Prior art systems place system memory into a self-refresh or a suspend-refresh state. Refresh is maintained by the memory itself or through some other reference clock that is not stopped during the sleeping (S1) state.
One example of a memory architecture is the Rambus® technology available from Rambus Corporation of Mountain View, Calif. Some Rambus® memories offer various power conservation modes (see “Direct Rambus™ Memory for Mobile PCs” also available from Rambus Corporation). Active, nap, standby, and PwrDown (powerdown) modes are available. An RDRAM® device automatically transitions to standby mode at the end of a transaction. When a memory transaction request is sent out to the memory array, the appropriate RDRAM® device exits standby and services the request.
Power consumption may be further reduced by placing RDRAM® devices in a nap mode or a powerdown mode. Nap and powerdown modes may be entered by sending commands to the memory. From both the nap mode and the powerdown mode, a resynchronization time is required by the RDRAM® devices for memory system's delay locked loop to synchronize the interface to the channel clock.
Unfortunately, these memory power conservation states do not directly map into power conservation states enumerated by the ACPI Specification. The system designer is left to determine which states to use at what time, and how to enter and exit such states. Particularly puzzling is how to perform re-initialization in such a memory architecture when exiting low latency states such as the ACPI S1 state where nap or powerdown memory power conservation modes are likely to be used.
When exiting nap and powerdown states, the memory requires clock re-initialization. Exiting the ACPI S1 state, however, typically results in returning directly to operating system code (in the memory subsystem) after deassertion of the STPCLK# interrupt. Accordingly, it may not be possible to execute low level software such as BIOS software in response to a transitions out of the S1 state. Consequently, the memory subsystem may not be sufficiently re-initialized to allow memory accesses to commence.